3.7 Low Cost 24 GHz Transceiver (Task 3.2)

A primary factor in the deployment of a Side Detection System (SDS) is the effort required to define final performance specifications and design a system that meets production cost targets. This task was structured to establish the requirements for a side detection system, to design a cost-effective sensor using MMIC based technology, and to verify the design by both on road and product assurance testing. The intent was to design a MMIC that was compatible with both the SDS and with a Rear Detection System (RDS) such that the same device could be used in both applications. The market strategy was to introduce the system for the commercial trucking industry and then extend the product to consumer automotive applications.

The task objectives are:

• Selection of a foundry process that supports low cost fabrication of 24 GHz MMIC devices.
• Refine and optimize the design so that performance parameters are centered around the foundry process parameters.
• Adapt system design and performance specification to foundry process capability.
• Finalize the design and fabricate multiple wafer runs to determine process variations.
• Submit final design to alternate foundries for quote.
• Build and demonstrate prototype systems using devices developed on this program.

3.7.1 MMIC Design Approach and Accomplishments

The design approach for the low cost transceiver was established and a vendor selected. The supplier was changing the standard process to a 4" diameter wafer line and to include scratch protection. This was a significant change from the initial development work on the 3" line. A first iteration was run to determine model changes associated with the new process. Tests indicated that changes were required on the MMIC circuit design. The first quarter milestone, design approach, and the second quarter milestone, first run of MMIC wafers, were completed ahead of schedule. The mask set was iterated to accommodate the new circuit and device models based on the new 4" process. Devices from 5 wafer runs were received during the first year. The first wafer run was prior to the inception of the ACAS Program contract and served as the baseline reference (3" design on 4" process). The plan included running wafers at different times to improve the design models, to determine the key processing parameters relative to RF performance, and to determine the variability of the process.

Characterization testing of the first four MMIC runs and characterization of MMICs in the final assembly over temperature was completed. All wafer runs completed during the first year were made from a "pizza" mask with four versions of Transmitter and four versions of Receiver chips.

A summary of MMIC performance for the four 4" wafer design runs fabricated from the developmental mask is shown in Table 3.14. As seen from the table, MMIC performance appears to be a function of gate length, and shorter gate length is not necessarily better in terms of overall performance. Even though the gain and maximum operating frequency (Ft) may be higher, the impedance characteristics of the devices change enough such that the interstage matching is inadequate and chip performance degrades. Additionally, we have not made enough wafer runs to determine chip performance for gate lengths longer than nominal. Minor design changes occurred between wafer runs, therefore care must be taken in reviewing the data and drawing conclusions regarding performance variations as a function of repeated wafer runs. Lot-to-lot variability will be correlated after the design is frozen.

The specifications for Tx and Rx isolations are the original engineering estimates of performance for the devices. These estimates were based on breaking down the overall system requirement into specifications for all components and leakage mechanisms in the system, including package leakage, antenna cross coupling, and MMIC leakage. Further investigation showed that the isolation is a strong function of the test fixture. It has been shown that the devices are within measurement accuracy of meeting the isolation specification when measured in a special fixture. It has also been shown that wafer level tests for isolation are invalid at this time. Integrated system tests, and further refinement of system performance parameters indicate that the overall system Tx to Rx isolation performance is being met with the devices as currently designed. These system level tests also indicate that the system isolation is being set by the integrated antenna assembly and not by the MMIC. At this time, it is expected that the individual chip specification can be changed, and no further redesign to improve isolation is planned.

A fifth wafer run of devices designed to vary gate length as a designed experiment parameter was made. Test data on the gate length experiment, as presented in table 3.15, shows predicted variability with regard to transmitter characteristics. The extremely low power on wafer #3 does not appear to be related to gate length and is discounted in the transmitter data analysis.

Note: The DC offset has been identified as a design problem that is highly susceptible to a "non-standard" process step. This process step was necessitated by the conversion to the new process and 4" line during Summer 1995. The transformer design on the mixer input is not compatible with the new foundry process, and a special step must be performed. This step is not well controlled (because it is non-standard), and appears to be a primary cause for both the magnitude and variability of the DC offset. The signal processor circuit card has been redesigned to accommodate the DC offset variability, but the receiver MMIC will require one more design iteration in order to eliminate the need for the "non-standard" step. This step has the potential to adversely affect the receiver gain, as well as, the DC offset.

All wafer runs during the first year were fabricated from the developmental "pizza" masks that contained multiple versions of the MMIC chips. Based on a review of all of the performance data, a final chip set was selected, and the mask was redone to include only this one chip set and associated process control monitor (PCM) sites.

Four wafers were fabricated from the production mask, and all appear to be acceptable based on DC PCM monitors. All four wafers have been RF tested at the wafer level for transmitter power and frequency, and appear to meet specification. The first wafer was delivered and had an overall yield of 70%, including yield losses due to DC, RF, and visual criteria. The remaining wafers are at the foundry awaiting RF testing of the receiver chip. Receiver chip wafer level RF test development is a part of the next quarter's planned activity. Efforts in the seventh quarter included developing an RF test for the receive MMICs. Three wafers were tested at the foundry for receive gain on one of the three receive channels, and one of these wafers was delivered for correlation tests in the system.

A total of 100 SDS prototype sensors were fabricated using the devices from the first production intent wafer. Although the fabrication cost for this volume of prototype SDS units are not a part of the ACAS program, the collection and analysis of MMIC performance data associated with these devices is necessary to determine the overall viability of the MMIC design. Transceiver performance data was measured over temperature at the microwave assembly. Twenty-nine performance parameters were measured at four temperatures, and the data from the eight deemed most critical was tabulated and analyzed statistically. As an example, the average transceiver loop gain, which is a function of transmitter power and receiver gain, has a 3 dB margin with regard to the specification limit, and has a standard deviation of 1 dB. All performance trends, including rates of change vs. temperature, tracked values that had been determined during the MMIC development and were consistent with the overall system design.

Twenty production units were assembled using MMICs from the final production mask for a designed experiment to determine the correlation between foundry data and system performance. MMICs were binned according to transmitter power and receive gain. Units were assembled to have different combinations of transmit power and receive gain, including combinations that should result in a lower than required system loop gain. The results of this experiment were very encouraging, in that it was shown that receive gain has a strong correlation with system loop gain, and that transmit power is a secondary effect. This result is not unexpected in that the transmitter is in gain compression, and less likely to vary over temperature, and the transmitter bin range was 1 dB. The receiver is operating in the linear region and the receiver bin range was 2 dB. Additionally, the receive gain is also a function of transmitter chip LO drive power, so the in-system receive gain is a function of both the chip level gain correlation and the difference between actual transmitter chip LO and a fixed MMIC test LO. It was determined from this test that the total number of receive bins could be reduced to 2, and that the need to bin transmitters may be eliminated in the future. It was also shown that RF screening at the MMIC level is viable for chips operating at this frequency.

3.7.2 SDS Sensor Fabrication and Test

Fabrication of SDS sensors using the MMICs fabricated as a part of the ACAS program was started. Sixty of these sensors were allocated for system qualification testing. Most of these qualification tests verify the integrity of the overall design and are not particularly stressful or directed toward the MMIC itself. Of particular interest to the ACAS program is the 1,000 hour powered temperature cycle life test. This tests the integrity of the MMIC and associated bonds and epoxy joints. The test has been split into two separate phases, an initial group of 10 and a second group of 15. This was done because a preliminary test on an early design iteration revealed a potential problem with a via design, and it was desirable to determine if the design change made to solve the problem was effective. The 10 units completed the 1,000-hour continuous powered temperature cycle with no failures associated with the MMIC design or fabrication. The second group completed testing in the sixth quarter. Final tests indicate one SDS unit had failed. The unit was submitted to failure analysis, and testing showed that the transmitter MMIC had failed. More extensive tests to determine the actual cause of failure were performed, but the root cause for the single transmitter failure could not be found. An additional 10 units were subjected to the powered temperature test and passed with no failures or measurable degradation. The qualification tests are 100% complete.

The units required for the last ACAS milestone associated with this task, vehicle demonstration, were completed and delivered for installation.

3.7.3 Challenges

Foundry Selection

An initial problem encountered was selection of the initial foundry. Operating frequency is dictated by Federal Communication Commission regulations regarding allowed operating frequency bands and associated power levels, and bands allowed as of January 1995 were 5.8, 10.525, and 24.125 GHz. The 5.8 and 10.125 GHz bands were not acceptable for the application due to antenna size restrictions imposed by the vehicle styling requirements. MMIC fabrication processes for gate formation are either photolithography or E-beam, and the general consensus is that E-beam is more expensive. Process tolerances are such that the less expensive photolithography process limits gate length to greater than 0.3 microns, and many foundries limit the process to greater than 0.5 microns. A gate length of 0.5 microns limits operating frequencies to less than 20 GHz. Therefore, the primary design had to be in a foundry that had a photolithography process that provided adequate gain at 24 GHz. This limited the number of foundries that were viable candidates. The initial foundry selected has performed well throughout the program, and the foundry process has been shown to be viable at 24 GHz in terms of performance, cost, and yield.

Design Compatibility

The only major problem relative to this task is the uncertainty of the final vehicle system application requirements. At the start of the ACAS Program, certain assumptions were made for both RDS and SDS system performance requirements. Specifically zones of coverage and target range reporting criteria are important parameters in selecting a system architecture. During the ACAS Program, the SDS specifications have not changed significantly, however, the RDS requirements have been very volatile. So volatile, that it is not certain that the original architecture chosen for the rear system is compatible with the new performance specifications as defined by the individual vehicle manufacturers. It is also not certain that the performance specification has yet stabilized. The MMIC design has been made to be compatible with both RDS and SDS requirements as initially defined, thus meeting the original ACAS Program objective of design compatibility between RDS and SDS. The specific task objectives were modified to concentrate on the SDS application and sensor development, even though the MMIC is compatible with the original RDS requirements and design architecture.

3.7.4 Completeness of Task and Major Benefits

This task was completed on schedule, but exceeded the original budget by 11%. The task overrun was projected early in the ACAS program, and was covered by reallocating funds from task 3.1. The task met all of the program goals and objectives as modified in the third quarter, which eliminated the demonstration of the MMICs in a rear detection system (RDS). The MMIC design met the intent of the original program objectives in that it was compatible with the RDS architecture and performance that was specified at the start of the program. (Reference Section 3.7.3)

The ACAS program enabled completion of a MMIC transceiver design that demonstrated good performance, high yields, and high reliability. The program provided the opportunity for multiple wafer runs in a short time frame that provided an adequate data base for design centering, wafer probe test correlation to system performance, and establishment of MMIC wafer probe acceptance test requirements. The MMICs were demonstrated in a side detection sensor that provided state of the art performance in road tests. Sensors using these devices passed stringent automotive product assurance tests. Sensors were also installed on a number of commercial trucks and accumulated hundreds of thousands of miles over all weather and road conditions.

3.7.5 Future Directions

There are challenges remaining with regard to successful implementation of side detection systems in automotive applications that were identified during the ACAS program, but are beyond the scope of the this task.

The number of foundries capable of meeting performance requirements using a cost-effective process is very limited at this frequency band. Although the foundry selected performed very well, the MMIC fabrication process is unique to that foundry, and the design would need to be modified for use in any alternate foundry. MMIC specifications were prepared and submitted to alternate foundries, but development costs for a second source were prohibitive. During the course of the ACAS program, significant progress has been made in process capability such that additional foundries are capable of meeting performance requirements. Adequate design building blocks must be developed at these foundries in order to minimize the non-recurring engineering development costs.

Automotive performance requirements for both side and rear detection systems must be defined and stabilized. Performance, styling issues, and cost targets changed significantly from the start of contract. This minimized the effectiveness of the program relative to immediate application of the technology and hardware developed. The ability to demonstrate MMIC feasibility, and to characterize the MMIC design and process was invaluable to the future of these types of sensors. As the application specifications mature and stabilize, the knowledge gained from this program can be effectively applied, and will reduce the development schedule and cost for these systems.